A low-density parity-check (LDPC) is a forward error correction code. By virtue of iterative decoding, coding is performed by using a pre-constructed spare check matrix. The LDPC code is excellent in terms of performance. However, since the conventional coding and decoding implementation method is very complicated, and is hard to be practiced on a hardware circuit, the LDPC code is restricted in application thereof.
To overcome the barrier of application of the LDPC code, Marc PC Fossorier proposes a quasi-cyclic low-density parity-check (QC-LDPC) code. The QC-LDPC code integrates the structural and random features, and greatly simplifies decoding circuitry while achieving the excellent performance of the LDPC code.
The QC-LDPC code simplifies the decoding circuitry. However, in the practical application scenario (for example, the QC-LDPC code has a great length), a QC-LDPC decoder still faces the difficulties of large occupation area of the chip, great demand on storage amount, complicated internal connection and high power consumption. Therefore, how to make a compromise between the decoding efficiency and resource consumption of the decoder, and how to better improve the data throughput of the decoder are still problems to be urgently solved.